1. Field of the Invention
The present invention relates generally to the sense amplifier circuit for a semiconductor memory device. More particularly, the present invention relates to a sense amplifier circuit and an associated read/write method adapted for use in a semiconductor memory device, the sense amplifier circuit being capable of amplifying and outputting data during a write mode and a read mode.
A claim of priority is made to Korean Patent Application No. 04-1814 filed on Jan. 10, 2004 in the Korean Patent Office. The disclosure of this Korean Patent Application is hereby incorporated by reference in its entirety.
2. Description of the Related Art
As semiconductor memory devices, for example the Rambus dynamic random access memory (RDRAM) or contemporary double data rate (DDR) DRAMs, become increasingly integrated and chip sizes increase, the length of global input and output (I/O) line pairs for transferring data to memory cells necessarily becomes longer. As a result, the line loads placed on these I/O line pairs during data transfer operations increase significantly.
In order to solve this problem, semiconductor memory devices typically include a sense amplifier circuit for amplifying data between the global I/O line pair and a local I/O line pair. The sense amplifier circuit amplifies data during a read operation to reduce a delay time, tDAC, thereby improving the read speed for the semiconductor memory device.
Delay time tDAC is the time it takes to deliver data from a memory core in the semiconductor memory device via the global I/O line pair and the global I/O line sense amplifier circuit to an external I/O line block after a read command has been generated.
FIG. 1 is a circuit diagram showing the structure of a conventional, local sense amplifier circuit. Within FIG. 1, local sense amplifier circuit 100 comprises first through fifth transistors TR1, TR2, TR3, TR4, and TR5 which function as amplification circuits between a local I/O line pair LIO and LIOB and a global I/O line pair GIO and GIOB.
In addition, local sense amplifier circuit 100 comprises sixth and seventh transistors TR6 and TR7 which function as switches for directly connecting the local I/O line pair LIO and LIOB with the global I/O line pair GIO and GIOB.
The sixth and seventh transistors TR6 and TR7 are turned on or off in response to a first control signal PWBBLK. The first transistor TR1 and the fourth and fifth transistors TR4 and TR5 are turned on or off in response to a second control signal PWBLK.
The first control signal PWBBLK is activated during a write operation of the semiconductor memory device and deactivated during a read operation of the semiconductor memory device.
On the contrary, the second signal PWBLK is activated during the read operation of the semiconductor memory device and deactivated during the write operation of the semiconductor memory device.
The term “activated” describes a signal state that assumes an active logic level, where the active logic level is a voltage which turns a transistor on. The term “deactivated” describes a signal state that assumes an inactive logic level, where the inactive logic level is a voltage which turns a transistor off.
During a read operation in the semiconductor memory device, the first transistor TR1 and the fourth and fifth transistors TR4 and TR5 are turned on when the second control signal PWBLK is activated. Since the first control signal PWBBLK is deactivated during a read operation, the sixth and seventh transistors TR6 and TR7 are turned off.
Suppose that during a read operation the local I/O line LIO receives an active logic level signal from the memory core (not shown in the drawing) and the inverted local I/O line LIOB receives an inactive logic level signal. In this case, the second transistor TR2 is turned on, the third transistor TR3 is turned off, and the first, second, and fourth transistors TR1, TR2, and TR4 form a current path allowing inverted global I/O line GIOB to receive an inactive logic level while the global I/O line GIO receives an active logic level.
Suppose instead that during a read operation the local I/O line LIO receives an inactive logic level signal from the memory core and the inverted local I/O line LIOB receives an active logic level signal. In this case, the first, third, and fifth transistors TR1, TR3, and TR5 form a current path allowing the global I/O line GIO to receive an inactive logic level signal while the inverted global I/O line GIOB receives an active logic level signal.
Therefore, during a read operation, signals present on the local I/O line LIO are amplified and output to the global I/O line GIO, and signals present on the inverted local I/O line LIOB are amplified and output to the inverted global I/O line GIOB.
During a write operation in the semiconductor memory device, sixth and seventh transistors TR6 and TR7 are turned on when the first control signal PWBBLK is activated. Since the second control signal PWBLK is deactivated, the first, fourth, and fifth transistors TR1, TR4 and TR5 are turned off.
Suppose that during a write operation the global I/O line GIO receives an active logic level signal from a source external to the semiconductor memory device and the inverted global I/O line GIOB receives an inactive logic level signal. In this case, the active logic level signal on the global I/O line GIO is delivered to the local I/O line LIO, and the low level data on the global I/O line GIOB is delivered to the inverted local I/O line LIOB.
Suppose instead that during a write operation the global I/O line GIO receives an inactive logic level signal from a source external to the semiconductor memory device and the inverted global I/O line GIOB receives an active logic level signal. In this case, the inactive logic level signal on the global I/O line GIO is delivered to the local I/O line LIO, and the active logic level signal on the global I/O line GIOB is delivered to the inverted local I/O line LIOB.
Therefore, during a write operation, signals present on the global I/O line GIO are amplified and output to the local I/O line LIO, and signals present on the inverted global I/O line GIOB are amplified and output to the inverted local I/O line LIOB.
The signals applied to the local I/O line pair LIO and LIOB are input to the memory core through a bitline (not shown in the drawing).
FIG. 2 is a waveform timing diagram showing a write operation of the local sense amplifier circuit in FIG. 1 and related operation of a bitline. In FIG. 2, the global I/O line GIO and the local I/O line LIO are shown, but the inverted global I/O line GIOB and the inverted local I/O line LIOB are omitted. In addition, delay times between signals are not considered in FIG. 2.
A wordline W/L is activated, and then a write data input to a write driver circuit (not shown in the drawing) is loaded on the global I/O line pair GIO and GIOB after a predetermined time. The write data is transferred when the global I/O line GIO transitions to an inactive logic level.
When the first control signal PWBBLK is activated, the sixth and seventh transistors TR6 and TR7 are turned on and the write data is transferred to the local I/O line pair LIO and LIOB.
The write data loaded on the local I/O line pair LIO and LIOB is transferred to the bitline pair BL and BLB while a column selection line CSL is activated.
However, due to the high degree of integration and increased chip sizes in contemporary semiconductor memory devices, the lengths of the global I/O line pair are so long that the resulting line loads increase to the point where the transfer of write data is unacceptably delayed.
In addition, as the internal operating frequency of semiconductor memory device increases, the pulse widths of internal operating signals decrease. In particular, as the pulse width of the column selection line CSL decreases, the time during which the column selection line CSL is activated during a write operation decreases as well. This creates a problem where write data on the local I/O line pair LIO and LIOB can not be accurately transferred to the bitline pair BL and BLB. This can be identified in the waveforms of the bitline pair BL and BLB shown in FIG. 2.